4 Art�culos

Understanding Timing Error Characteristics from Overclocked Systolic Multiply?Accumulate Arrays in FPGAs

Acceso

en l�nea

Andrew Chamberlin, Andrew Gerber, Mason Palmer, Tim Goodale, Noel Daniel Gundi, Koushik Chakraborty and Sanghamitra Roy

Artificial Intelligence (AI) hardware accelerators have seen tremendous developments in recent years due to the rapid growth of AI in multiple fields. Many such accelerators comprise a Systolic Multiply?Accumulate Array (SMA) as its computational brain. ... ver m�s

Revista: Journal of Low Power Electronics and Applications Formato: Electr�nico

Tabla de contenido: Vol: 14 Num: 0 Par: 1 A�o: 2024

Implementing a Timing Error-Resilient and Energy-Efficient Near-Threshold Hardware Accelerator for Deep Neural Network Inference

Acceso

en l�nea

Noel Daniel Gundi, Pramesh Pandey, Sanghamitra Roy and Koushik Chakraborty

Increasing processing requirements in the Artificial Intelligence (AI) realm has led to the emergence of domain-specific architectures for Deep Neural Network (DNN) applications. Tensor Processing Unit (TPU), a DNN accelerator by Google, has emerged as a... ver m�s

Revista: Journal of Low Power Electronics and Applications Formato: Electr�nico

Tabla de contenido: Vol: 12 Num: 0 Par: 2 A�o: 2022

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