Fast State-of-Charge-Balancing Strategy for Distributed Energy Storage Units Interfacing with DC–DC Boost Converters

Abstract

State-of-charge balance is vital for allowing multiple energy storage units (ESUs) to make the most of stored energy and ensure safe operation. Concerning scenarios wherein boost converters are used as the interfaces between ESUs and loads, this paper proposes a balancing strategy for realizing consistent state-of-charge (SoC) levels and equal currents among different ESUs. This strategy is valid for both parallel and series applications. Its advantages also include its high precision of SoC equalization without extra sensors and fast convergence. A common outer voltage loop is used to accomplish tight voltage regulation, while multiple inner current loops are utilized to achieve current control and SoC balance simultaneously. Firstly, by introducing SoC-based current distribution ratios (CDRs) to modify current references online, the currents are gradually adjusted to eliminate SoC deviations. Secondly, to expedite the balancing process, current saturations are further adopted. Thirdly, the influences of accelerating factor and current limits in CDR expressions are analyzed, and their selection guidelines are subsequently provided. Fourthly, the controller design, consisting of a dual loop, is illustrated to guarantee sufficient stability margins. Fifthly, an experimental platform consisting of three battery ESUs is developed to verify the proposed strategy.

1. Introduction

Regarded as a key component of future power networks [1], a microgrid consists of renewable energy resources, energy storage systems (ESSs), and loads. Compared with AC microgrids, DC microgrids are superior in terms of efficiency, synchronization, and harmonics [2]. Thus, more and more attention is being paid to DC microgrids. The general configuration of a DC microgrid is shown in Figure 1. The inherent intermittency of renewable energy resources has negative effects on power quality and system stability. A battery ESS is usually used to mitigate this problem. It commonly contains an energy storage unit (ESU), a battery management system, and a power converter unit (PCU). Popular batteries used in microgrids are briefly described as follows: (1) Lead–acid batteries are cheap, but their specific energy is low. (2) Ni-Cd batteries have high power density and a long service life, but their memory effect is undesired, and they pollute the environment. (3) Ni-MH batteries are environmentally friendly and their self discharge is low, but their high price reduces their competitiveness. (4) Li-ion batteries have desired voltage platforms, long cycle life, and a wide temperature range, but technical protections are essential to prevent overuse. In fact, there exists a common issue for diverse batteries wherein the mismatches of internal impendence, self-discharge rate, and temperature cause imbalanced state-of-charge (SoC) levels in battery cells or ESUs. To fully use the rated capacities of batteries and prolong their lifetimes, effective solutions are needed for SoC equalization. So far, balancing topologies and balancing control strategies are the two categories of methods for eliminating SoC deviations.

Balancing topologies mainly include the dissipative and non-dissipative types [3]. The former transfers excess energy to heat in power resistors. It is a simple approach, but it is only applicable to the charging process, and considerable energy losses are inevitable. The latter type adopts active balancing circuits to redistribute excess energy. Numerous balancing topologies with different virtues have been presented, such as multi-winding transformers [4], switched-capacitor circuits [5], LC resonant circuits [6] and non-inverting buck–boost circuits [7]. Favorable balancing results can be achieved, but the system costs increase.

As for the control algorithms used to realize a consistent SoC, there are two main kinds, namely, the centralized and decentralized types. To accomplish centralized control, a central controller [8,9] is employed to coordinate the sources, ESSs, and loads in real time. Nevertheless, potential single-point failures decrease system reliability [10].

Decentralized methods reduce dependence on communications and therefore enhance system reliability. As typical representatives of decentralized methods, plenty of SoC-based droop control schemes have been investigated. Due to virtual damping and inertia, the transient stability of dc-bus voltage was improved after a bidirectional dc-dc circuit was equivalently converted to an equivalent virtual dc machine in [11]. However, the line resistances and voltage drops were ignored, so the actual accuracy of SoC equalization deteriorated to some extent. In [12], SoC levels, line impedances, and virtual power ratings were all considered to achieve accurate power sharing. But five PI regulators were needed for each PCU, thus increasing implementation complexity. In [2], the droop coefficient was inversely proportional to the high-order term of the local SoC. Free from communications, power sharing and SoC balance were gradually obtained. Nevertheless, voltage deviation was inescapable, though it was constrained by choosing a proper exponent. Balancing speed is a vital index for balancing control. In [13], the adaptive virtual resistances were applied to flexibly adjust the power and status of ESUs for the rapid elimination of SoC errors. In [14], the relationship of the arctangent function is determined between droop coefficients and the individual SoC for faster SoC balancing. However, the overall scheme involves multiple control loops, and this is quite inconvenient for controller design. In [10], the reference voltage and virtual impedance were devised as two piecewise functions of local SoC so that coordinated operation could be achieved between ESSs and the utility grid. Moreover, I-V SoC-based droop approaches have also been applied to inner current loops for better dynamic response [15,16]. Deriving from inverse droop, the balancing method in [17] adaptively modifies the reference voltage by adjusting the frequency–power curve. But power losses are also neglected for SoC estimation. Through sparse communication, three-layer hierarchical control schemes [18,19] have been presented to cope with the issues of bus voltage deviation and inconsistent line resistances. But additional balancing factors [18] or control loops [19] require an elaborate design to ensure system stability.

Some active balancing strategies are also used to achieve SoC consistency. For hybrid ESSs with different parameters, the event-triggered control theory was used to acquire balanced SoC levels in [20]. But complex principles may cause inconvenience for engineering applications. Based on the remaining energy of all batteries and the output signal of the voltage loop, a common time reference was produced to indirectly change the individual reference currents for an equal SoC in [21]. For modular multilevel ESSs, SoC balance was accomplished by directly adjusting the reference currents of inner loops in [22]. But large-signal stability analysis should also be provided for proper controller design because the supercapacitor voltages decrease obviously during the balancing process. For output-series hybrid ESSs, the cooperative control of a three-port converter was studied in [23]. The problems of imbalanced SoC and voltages are addressed, while excellent transient performance cannot be guaranteed in the absence of an inner current loop.

A simple structure, high efficiency, and boosted output voltage are the main virtues of dc-dc boost converters, leading to their extensive applications in microgrids. Based on interfacing boost converters, the novel contributions of this article are summarized as follows:

(1)

A SoC-balancing strategy based on the current distribution ratio (CDR) is presented for multiple ESUs interfacing with boost converters by adjusting the reference currents.

(2)

Current saturation is used to shorten the SoC equalization time by fully utilizing the current capability and enabling a large accelerating factor. The impacts of current limits and the accelerating factor are analyzed, and their selection rules are provided.

(3)

The controller design is given to guarantee sufficient margins during discharge.

(4)

The adaptive current limits that vary in proportion to the sum current are utilized for series applications to prevent unexpected step reference currents under conditions of load change.

Comparisons with representational balancing methods are listed in

Table 1. Comparisons with the existing balancing methods.

Balancing Method	Suitable Application	Style of SoC Estimation	Accuracy of SoC Estimation	Number of Voltage Sensors	Number of Current Sensors	Total Number of Sensors	Sensor Cost
[1]	parallel	calculation	High	m	2m	3m	High
[2]	parallel	approximation	Not high	2m	2m	4m	High
[10]	parallel	approximation	Not high	m	m	2m	High
[15]	series	calculation	High	1	m + 1	m + 2	Not high
[17]	series	approximation	Not high	m	2m	3m	High
[22]	series	approximation	Not high	m + 1	1	m + 2	Not high
proposed	both	calculation	High	1	m	m + 1	Low

m is the number of ESUs (or PCUs).

. The main advantages of this strategy are described below:

(1)

High Precision of SoC Equalization without Extra Sensors: In boost converters, the inductor current is also the ESU current. Instead of approximate estimation, these two currents are precisely measured by a single current sensor in each PCU. Then, the real-time SoC can be directly calculated after the initial SoC is determined. This makes the proposed strategy a cost-effective solution for accurate SoC equalization.

(2)

Applicability for Parallel and Series Scenarios: In parallel scenarios, this strategy distributes the load current to mitigate SoC deviations. In series scenarios, it regulates individual voltage gains for SoC consistency while the sum voltage is unchanged.

(3)

Accelerated Balancing Process: The current capacity of the converter is fully exploited by introducing saturation. Thus, high current deviations are maintained for a long time, and this leads to the fast elimination of SoC differences. Moreover, the large accelerating factor in the approaching law is enabled by saturation, and high convergence speed is thereupon activated after some ESUs cease being saturated.

2. Proposed SoC-Balancing Strategy without Saturation

Usually, an ESU consists of some cells connected in series or parallel. To remove the potential SoC differences among ESUs, a SoC-balancing strategy based on the CDR is presented in this paper. Note that the SoC balance among battery cells is not the concern of this paper.

2.1. Basic Principle of SoC-Balancing Strategy

If boost converters function as the interfaces between distributed ESUs and loads, they are actually independent of the input side and parallel (or series) circuit connected on the output side. Owing to this feature, the individual SoC can be regulated by its own PCU. The corresponding configuration is outlined in Figure 2, where the ESUs are batteries. Inductor L_k, power switch S_k and diode D_k constitute the PCU#k, where k = 1, 2, …, m. Capacitor C and load R are shared by the PCUs on the output side. The input voltage of PCU#k is denoted as u_ik. Moreover, u_dc and i_o are the dc-bus voltage and load current, respectively.

As seen in Figure 3, dual-loop control is used to coordinate multiple units. A common outer loop is used for voltage regulation, while multiple inner loops are used for current control and SoC equalization. Here, i_rk, i_k, d_k, and CDR_k are reference current, feedback current, duty cycle, and the current distribution ratio of the PCU#k, respectively.

The parallel form helps to enhance system capacity, while the series form enables applications at higher voltage levels. In terms of discharge, the proposed method is valid for both parallel and series applications. When the PCUs are paralleled on the output side, u_dc is constant, and thus the load current can be reasonably distributed by CDRs according to the individual SoC level. When the PCUs are connected in series, the load current is unchanged and shared by all units. Then, the individual output voltages can be flexibly regulated while u_dc is fixed. In fact, the individual voltage gains are modified little by little, and the phase currents thereupon vary towards a consistent SoC status. To fulfill this strategy, the CDRs are introduced, which are expressed as

$$CD{R}_k=\frac{So{C}_k^n}{{\displaystyle {\sum }_{k=1}^{m}So{C}_k^n}},k=1,2,\cdot \cdot \cdot ,m$$

(1)

where n is an accelerating factor used to shorten the SoC-balancing duration. The output of the voltage regulator is the common input of all the current loops and acts as the reference of the sum current i_sum. The product of i_sum and CDR_k is the current reference of PCU#k, which is expressed as

$$i_{\mathrm{r}k}=i_{\mathrm{sum}}\times CD{R}_k$$

(2)

Then, the error between reference and feedback is processed by the current regulator to produce the duty cycle of each PCU. Thus, we can adjust the current distribution according to the relative value of the SoC so that individual states of charge are forced to be identical. On the one hand, lower current is anticipated for the ESU with a lower SoC to slow down the SoC decrease. On the other hand, a higher current is expected for the ESU with a higher SoC in order to expedite the SoC decrease. If these conditions are met, the SoC deviations will gradually be reduced, and the same SoC level will eventually be shared by all the ESUs. In the meantime, the currents of different PCUs become closer and closer. Furthermore, current sharing is achieved once a consistent SoC is obtained, according to Figure 3.

2.2. Estimation of SoC

SoC estimation is expressed as

$$So{C}_k=So{C}_{k0}-\frac{{\displaystyle \int i_{k}dt}}{Q},k=1,2,\cdot \cdot \cdot ,m$$

(3)

where Q is the rated capacity of the ESU and SoC_k0 is the initial SoC level of ESU#k. To make the best of the coulomb-counting method and the open-circuited voltage (OCV) method [24], a joint method is used here to estimate SoC. The latter is used to obtain the initial SoC, while the former is employed to calculate the depth of discharge.

In this paper, the ESUs are lead–acid batteries, and the rated voltage is 12 V. Based on actual data, the characteristic curve of OCV versus SoC is plotted in Figure 4. Using the polynomial style to perform curve fitting, the relationship can be formulated as follows:

$$OCV=0.5692\times So{C}^3-1.14\times So{C}^2+1.765\times SoC+11.11$$

(4)

2.3. Selection of the Accelerating Factor in CDRs

To be convenient and general, m is set as 3 in this paper. Then, the value of n is discussed in detail. At first, n should be a positive integer to reduce the computing burden of the microprocessors. Assuming that each phase current can follow its reference immediately, this is an ideal case. Combining Equations (1)–(3), the ideal curves with the proposed strategy in parallel applications are plotted in Figure 5 when i_sum remains constant. The system parameters are given in

Table 2. Key system parameters.

Parameters	Symbol	Value
Switching frequency	fs	20 kHz
Inductance	L1, L2, L3	4 mH
Capacitance	C	2200 uF
Load current	io	20 A (parallel)
		6 A (series)
DC-bus voltage	udc	30 V (parallel)
		90 V (series)
Initial SoC	SoC10; SoC20; SoC30	0.9; 0.8; 0.7
Battery capacity	Q	45 Ah
Magnitude of carrier waves	Am	37,500
Proportional gain of voltage loop	kpv	0.5
Integral gain of voltage loop	kiv	5
Proportional gain of current loop	kpi	1000
Integral gain of current loop	kii	10,000

. Under the same conditions, n mainly affects the balancing time and initial current distribution. If a higher value of n is used, the required time to realize SoC consistency is shorter, but the ESU with a higher SoC releases a higher current, and this threatens the safe operation of the relevant unit. For the shortest balancing time, it is essential to confirm the maximum n. Its selection process is described as follows.

In parallel scenarios, the upper limitation of n is governed by i_allow, the maximum allowable current of the PCU. For our testing platform, the allowable currents of the power switch, battery, and inductor are 120 A, 450 A, and 40 A, respectively. Thus, i_allow is set as 40 A to ensure the safe operation of the overall system. Then, n should satisfy the following inequality:

$$\frac{\max (So{C}_{k0}^n)}{{\displaystyle {\sum }_{k=1}^{m}So{C}_{k0}^n}}\times i_{\mathrm{sum}}\times (1+\eta )<i_{\mathrm{allow}}$$

(5)

where max( ) is the maximum function. Positive η is a margin coefficient used to prevent overcurrent in real applications. Here, the actual upper limit of the current i_allow/(1 + η) is denoted as i_satu. According to Figure 5, the highest peak current appears at the initial stage of discharge. Then, i_sum can be roughly estimated according to energy conservation. Here, i_sum is 50 A, and η = 0.2. Consequently, i_satu is 33 A, and the maximum n is 8.

As for series scenarios, the load current in a boost converter also serves as the lower limit of the phase currents, i_satl. Thus, both i_satu and i_satl should be considered to achieve a maximum n. In a system with three units, it is evident that 3i_satl $\le$ i_sum $\le$ 3i_satu. Besides Inequation (5), the following restriction also needs to be fulfilled, which is expressed as

$$i_{\mathrm{sum}}\times \frac{\min (So{C}_{k0}^n)}{{\displaystyle {\sum }_{k=1}^{m}So{C}_{k0}^n}}\ge i_{\mathrm{satl}}$$

(6)

where min( ) is the minimum function. Combing Inequation (6) with Inequation (5), the maximum n is 5 when i_sum = 45 A and i_satl = 6 A. Due to the similarity of the ideal curves in the two applications, the corresponding curves in series applications are omitted.

3. Enhanced SoC-Balancing Strategy with Saturation

In the strategy in Section 2, the high current deviations only last for a short time. While the discharge process continues, the SoC differences become low, and then the approaching speed decreases rapidly. Although this strategy is brief and clear, it sacrifices more time to reach the balanced point. To accelerate the balancing process, current saturations are further utilized to enhance the aforementioned strategy.

For parallel scenarios, the preprocessed current reference is set as i_satu if it exceeds i_satu. Moreover, the rest of i_sum is redistributed by the other unsaturated units according to their own SoC levels. As the equalization process continues, the units with a higher SoC will desaturate one by one. As for series scenarios, i_o provides an inherent lower limit for the phase currents in boost converters. Therefore, i_k is increased to i_satl if it is lower than i_satl.

This improved strategy enables the usage of a larger n. During the initial stage, the high current deviations are maintained for a longer duration, so the eliminating rate of SoC deviations is high. When the ESUs are no longer saturated, a larger n leads to a faster balancing process that resembles a power function. In view of these two factors, current saturations can expedite the entire balancing process.

3.1. Expressions of CDRs

Above all, we assume that SoC₁₀ > SoC₂₀ > SoC₃₀. Moreover, some intermediate variables are needed, and they are defined as follows:

$$\left\{\begin{array}{c}CD{R}_{11}=So{C}_1^n/(So{C}_1^n+So{C}_2^n+So{C}_3^n)\\ CD{R}_{12}=So{C}_2^n/(So{C}_1^n+So{C}_2^n+So{C}_3^n)\\ CD{R}_{13}=So{C}_3^n/(So{C}_1^n+So{C}_2^n+So{C}_3^n)\\ \begin{array}{c}CD{R}_{22}=(1-i_{\mathrm{satu}}/i_{\mathrm{sum}})\times So{C}_2^n/(So{C}_2^n+So{C}_3^n)\\ CD{R}_{23}=(1-i_{\mathrm{satu}}/i_{\mathrm{sum}})\times So{C}_3^n/(So{C}_2^n+So{C}_3^n)\\ CD{R}_{31}=(1-i_{\mathrm{satl}}/i_{\mathrm{sum}})\times So{C}_1^n/(So{C}_1^n+So{C}_2^n)\\ CD{R}_{32}=(1-i_{\mathrm{satl}}/i_{\mathrm{sum}})\times So{C}_2^n/(So{C}_1^n+So{C}_2^n)\end{array}\end{array}\right.$$

(7)

Figure 6a gives the flow path used to assign CDRs in series applications, and it is performed once in each control period. Detailed expressions of CDRs are listed in

Table 3. Expressions of CDRs with saturation.

Case	g	h	CDR1	CDR2	CDR3
1	0	0	CDR11	CDR12	CDR13
2	1	0	isatu/isum	CDR22	CDR23
3	2	0	isatu/isum	isatu/isum	1 − 2isatu/isum
4	0	1	CDR31	CDR32	isatl/isum
5	0	2	1 − 2isatl/isum	isatl/isum	isatl/isum
6	1	1	isatu/isum	1 − (isatu + isatl)/isum	isatl/isum

. Here, g and h are the unit amounts at the upper and lower saturations. The main workflow is summarized in three steps. Firstly, the judging conditions are used to confirm the values of g and h. Secondly, the current distributions of all the units are kept within an allowable range again. Finally, the CDRs are assigned according to the specific case. The assigning task in parallel applications is shown in Figure 6b. Compared with that in series applications, it is regarded as a simplified version, setting i_satl = 0 and h = 0. In fact, its expressions of CDRs correspond to the first three cases in Table 3.

3.2. Selection of the Accelerating Factor in CDRs

With an increasing n, the related execution time of CDR calculation is prolonged. As the duration required to execute entire program in the microprocessors must be shorter than the control period, n cannot be too large. This is indicated by

$$t_{\mathrm{else}}+n\times t_{\mathrm{mul}}<t_{\mathrm{ctrl}}$$

(8)

where t_mul is the required time of a single multiplication and t_else is the rest time of the whole program. Moreover, t_ctrl is the control period; here, it is equal to the switching period. The closed-loop control and data communications are accomplished using DSP28335 chips. The power function can be used to calculate high-order terms of SoC, but it takes much more time than continuous multiplication. Thus, continuous multiplication was utilized to reduce the execution time. Based on Inequation (8), the maximum n is confirmed.

Under the enhanced strategy, the minimum n for parallel applications should make g $\ge$ $1$ so that the current capacity of the converter is fully utilized. If i_sum − i_satu < i_satu, that is, i_sum < 2i_satu, the following requirement should be satisfied:

$$\frac{\max (So{C}_{k0}^n)}{{\displaystyle {\sum }_{k=1}^{m}So{C}_{k0}^n}}\times i_{\mathrm{sum}}>i_{\mathrm{satu}}$$

(9)

The ESU current with lowest SoC_k0 decreases when n increases. But it cannot be lower than the least significant current (LSC), which is decided by the range of current sensor and the bit number of analog-to-digital converter in microprocessors. The maximum n should correspond to the following:

$$(i_{\mathrm{sum}}-i_{\mathrm{satu}})\times \frac{So{C}_3^n}{So{C}_2^n+So{C}_3^n}>1 \mathrm{LSC}$$

(10)

Inequations (8) and (10) are both considered for a maximum n.

If i_sum − i_satu > i_satu, that is, i_sum > 2 i_satu, it is possible that two units are saturated. To establish the above situation, the minimum n can be found, which is formulated as

$$CD{R}_{11}{|}_{t=0}> i_{\mathrm{satu}}/i_{\mathrm{sum}},CD{R}_{22}{|}_{t=0}> i_{\mathrm{satu}}/i_{\mathrm{sum}}$$

(11)

In addition, the maximum n is derived according to Inequation (8).

As for series applications, the minimum n should let $\mathit{g}+\mathit{h}=2$ so that the high current deviations help shorten the balancing duration. In Figure 6a, four potential paths exist, and they are separately expressed as

$$CD{R}_{11}{|}_{t=0}> i_{\mathrm{satu}}/i_{\mathrm{sum}},CD{R}_{22}{|}_{t=0}> i_{\mathrm{satu}}/i_{\mathrm{sum}}$$

(12)

$$\left\{\begin{array}{c}CD{R}_{11}{|}_{t=0}\le i_{\mathrm{satu}}/i_{\mathrm{sum}},CD{R}_{13}{|}_{t=0}< i_{\mathrm{satl}}/i_{\mathrm{sum}}\\ CD{R}_{32}{|}_{t=0}< i_{\mathrm{satl}}/i_{\mathrm{sum}}\end{array}\right.$$

(13)

$$\left\{\begin{array}{c}CD{R}_{11}{|}_{t=0}>i_{\mathrm{satu}}/i_{\mathrm{sum}}\\ CD{R}_{22}{|}_{t=0}< i_{\mathrm{satu}}/i_{\mathrm{sum}},CD{R}_{23}{|}_{t=0}< i_{\mathrm{satl}}/i_{\mathrm{sum}}\end{array}\right.$$

(14)

$$\left\{\begin{array}{c}CD{R}_{11}{|}_{t=0}\le i_{\mathrm{satu}}/i_{\mathrm{sum}},CD{R}_{13}{|}_{t=0}< i_{\mathrm{satl}}/i_{\mathrm{sum}}\\ CD{R}_{32}{|}_{t=0}\ge i_{\mathrm{satl}}/i_{\mathrm{sum}},CD{R}_{31}{|}_{t=0}>i_{\mathrm{satu}}/i_{\mathrm{sum}}\end{array}\right.$$

(15)

In fact, only one of the above four expressions is feasible if a specific set of i_sum, SoC_k0, and current limits is adopted. And Inequation (8) is applied to acquire maximum n.

3.3. Selection of the Current Limits in CDRs

If the enhanced strategy is used for parallel applications, i_satu cannot be too low. It should satisfy the following:

$$\frac{i_{\mathrm{satu}}}{i_{\mathrm{sum}}}>\frac{So{C}_{10}}{So{C}_{10}+So{C}_{20}+So{C}_{30}}$$

(16)

Otherwise, the equilibrium point is not reachable before the SoC reaches zero.

When i_sum < 2i_satu, only one ESU may be saturated, namely, ESU#1. The other two ESUs are equalized at the very start. Then, the two currents correspond to

$$i_2=(i_{\mathrm{sum}}-i_{\mathrm{satu}})\times \frac{So{C}_3^n}{So{C}_3^n+So{C}_2^n},i_3=(i_{\mathrm{sum}}-i_{\mathrm{satu}})\times \frac{So{C}_3^n}{So{C}_3^n+So{C}_2^n}$$

(17)

After ESU#2 and ESU#3 are balanced, CDR₁₁ should continuously decrease until reaching 1/3 and the equalization of the three ESUs is acquired. The slope of CDR₁₁ is calculated as

$$\left\{\begin{array}{c}CD{R}_{11}^{\prime }=\frac{nSo{C}_1^{n-1}[ASo{C}_2^{n-1}+BSo{C}_3^{n-1}]}{{(So{C}_1^n+So{C}_2^n+So{C}_3^n)}^2}\\ A=So{C}_{2}So{C}_1^{\prime }-So{C}_{1}So{C}_2^{\prime },B=So{C}_{3}So{C}_1^{\prime }-So{C}_{1}So{C}_3^{\prime }\end{array}\right.$$

(18)

where ‘$\prime$’ is a time-derivative operator. The following is introduced:

$$\left\{\begin{array}{c}So{C}_2=So{C}_3\\ So{C}_2^{\prime }=So{C}_3^{\prime }=-(i_{\mathrm{sum}}-i_{\mathrm{satu}})/(2Q)\\ So{C}_1^{\prime }=-i_{\mathrm{satu}}/Q\end{array}\right.$$

(19)

Afterwards, the numerator of Equation (18) is deduced as follows:

$$\mathrm{num}(CD{R}_{11}^{\prime })=nSo{C}_1^{n-1}So{C}_2^{n-1}[i_{\mathrm{sum}}\times So{C}_1-i_{\mathrm{satu}}(So{C}_1+So{C}_2+So{C}_3)]/Q$$

(20)

Thus, the reachable restriction is represented as

$$\frac{i_{\mathrm{satu}}}{i_{\mathrm{sum}}}>\frac{So{C}_1}{So{C}_1+So{C}_2+So{C}_3}$$

(21)

Accordingly, CDR₁₁ will decline. To actualize Inequation (21), the maximum of the right side needs to be found. In fact, it persistently drops until reaching 1/3, as the individual SoC levels come closer and closer under the balancing control. Thus, its maximum is just the initial value. Undoubtedly, Inequation (21) is guaranteed if only Inequation (16) is realized.

When i_sum > 2i_satu, ESU#1 and ESU#2 are saturated in the beginning. With the SoC levels approaching each other, ESU#2 becomes unsaturated earlier, and the following condition is met:

$$(i_{\mathrm{sum}}-i_{\mathrm{satu}})\times \frac{So{C}_2^n}{So{C}_2^n+So{C}_3^n}=i_{\mathrm{satu}}$$

(22)

By simplifying Equation (22), we have

$$\frac{So{C}_3}{So{C}_2}=\sqrt[n]{\frac{i_{\mathrm{sum}}}{i_{\mathrm{satu}}}-2}=w\in (0,1]$$

(23)

Then, i₂ = i_satu and i₃ = i_sum − 2i_satu. Combination with Equation (3) yields

$$t_0=\frac{Q(wSo{C}_{20}-So{C}_{30})}{(w+2)i_{\mathrm{satu}}-i_{\mathrm{sum}}}<\min (\frac{QSo{C}_{30}}{i_{\mathrm{sum}}-2i_{\mathrm{satu}}},\frac{QSo{C}_{20}}{i_{\mathrm{satu}}})$$

(24)

Equation (23) implies that i_sum = (2 + wⁿ) i_satu < (2 + w) i_satu. Moreover, we determined that w = SoC₃/SoC₂ > SoC₃₀/SoC₂₀ as i₂ > i₃. Thus, t₀ is positive. Another question is whether the moment t₀ occurs before SoC₂ and SoC₃ decrease to zero as Inequation (24) states. This restriction is assumed correct, and then the balancing operation begins between ESU#2 and ESU#3. After the SoC levels of the two ESUs are identical, the situation is the same as that when i_sum < 2i_satu. Three balanced ESUs can be obtained once Inequation (16) is met. Based on Inequations (16) and (24), it is inferred that

$$\frac{i_{\mathrm{sum}}-2i_{\mathrm{satu}}}{(w+2)i_{\mathrm{satu}}-i_{\mathrm{sum}}}<\frac{So{C}_{20}+So{C}_{30}-So{C}_{10}}{(w+1)So{C}_{10}-So{C}_{20}-So{C}_{30}}<\frac{So{C}_{30}}{wSo{C}_{20}-So{C}_{30}}$$

(25)

Therefore, it is ensured that t₀ < Q ∗ SoC₃₀/(i_sum − 2i_satu). For convenient analysis, auxiliary function f₁(x) is defined as

$$f_1(x)={(\sqrt[n]{x-2}+2-x)}^{-1},x=i_{\mathrm{sum}}/i_{\mathrm{satu}}\in (2,3]$$

(26)

In fact, f₁(x) is positive, and it increases when x increases. Based on Inequation (16), the following relationship can be deduced:

$$\frac{i_{\mathrm{satu}}}{(w+2)i_{\mathrm{satu}}-i_{\mathrm{sum}}}<\frac{So{C}_{10}}{(w+1)So{C}_{10}-So{C}_{20}-So{C}_{30}}$$

(27)

Also, f₂(y) is defined as follows

$$f_2(y)=\frac{y}{(w+1)y-So{C}_{20}-So{C}_{30}},y=So{C}_{k0}\in (0,1]$$

(28)

In fact, f₂(y) decreases while y increases, thus proving that

$$\frac{So{C}_{10}}{(w+1)So{C}_{10}-So{C}_{20}-So{C}_{30}}<\frac{So{C}_{20}}{wSo{C}_{20}-So{C}_{30}}$$

(29)

Combining Inequation (27) with Inequation (29), we attain the following: t₀ < Q ∗ SoC₂₀/i_satu. In brief, the assumption in Inequation (24) is true as long as Inequation (16) is established.

In series scenarios, the minimum i_satu is the same as that in parallel scenarios. However, there exists an upper limit i_satuu for i_satu. If i_satu exceeds i_satuu, a step change in the reference current will appear when some ESUs become desaturated. Furthermore, this leads to the deterioration of u_dc in actual systems. To improve power quality, this phenomenon ought to be avoided.

According to Equation (7), CDR₁₁ decreases and CDR₂₃ increases after the balancing strategy is enabled. If CDR₁₁ drops to i_satu/i_sum after CDR₂₃ increases to i_satl/i_sum, the unexpected step reference current is actually averted, which is expressed as

$$CD{R}_{11}{|}_{t=t_1}=i_{\mathrm{satu}}/i_{\mathrm{sum}},CD{R}_{23}{|}_{t=t_2}=i_{\mathrm{satl}}/i_{\mathrm{sum}},t_1\ge t_2$$

(30)

Suppose that n is large enough to make each phase current constant in the beginning. If i_satl < i_sum − i_satu − i_satl < i_satu, three currents are separately distributed as

$$i_1=i_{\mathrm{satu}},i_2=i_{\mathrm{sum}}-i_{\mathrm{satl}}-i_{\mathrm{satu}},i_3=i_{\mathrm{satl}}$$

(31)

By substituting Equation (31) into CDR₂₃, we have

$$(1-\frac{i_{\mathrm{satu}}}{i_{\mathrm{sum}}})\times \frac{So{C}_3^n(t_1)}{So{C}_2^n(t_1)+So{C}_3^n(t_1)}=\frac{i_{\mathrm{satl}}}{i_{\mathrm{sum}}}$$

(32)

Combining Equations (3), (31), and (32) yields

$$t_1=\frac{\sqrt[n]{(i_{\mathrm{sum}}-i_{\mathrm{satu}}-i_{\mathrm{satl}})/i_{\mathrm{satl}}}\times So{C}_{30}-So{C}_{20}}{\sqrt[n]{(i_{\mathrm{sum}}-i_{\mathrm{satu}}-i_{\mathrm{satl}})/i_{\mathrm{satl}}}\times i_{\mathrm{satl}}-i_{\mathrm{sum}}+i_{\mathrm{satu}}+i_{\mathrm{satl}}}\times Q$$

(33)

To obtain the critical i_satu in Equation (30), replace t₂ with t₁. After combination with Equation (31), CDR₁₁ is rewritten as

$$\frac{{[So{C}_{10}-i_{\mathrm{satu}}{t}_1/Q]}^n}{{[So{C}_{20}-(i_{\mathrm{sum}}-i_{\mathrm{satu}}-i_{\mathrm{satl}})t_1/Q]}^n+{[So{C}_{30}-i_{\mathrm{satl}}{t}_1/Q]}^n}=\frac{i_{\mathrm{sum}}-i_{\mathrm{satu}}}{i_{\mathrm{satu}}}$$

(34)

An analytical solution is hard to acquire, as Equation (34) is a high-order equation about i_satu. Instead, tool software can be used to facilitate the solving procedure. Then, a numerical solution can be obtained, and that is exactly the value of i_satuu.

When load change occurs, i_satl and i_satu require proper adjustment so that the equilibrium point is still accessible and the step current references are escapable. According to energy conservation, i_sum varies in the same direction and proportion when i_o suddenly changes. That is to say, the variation in i_sum directly reflects the variation in i_o. Accordingly, i_satl and i_satu are rearranged as

$$i_{\mathrm{satu}}=i_{\mathrm{satu}0}\times i_{\mathrm{sum}}/i_{\mathrm{sum}0},i_{\mathrm{satl}}=i_{\mathrm{satl}0}\times i_{\mathrm{sum}}/i_{\mathrm{sum}0}$$

(35)

where i_sum0, i_satu0, and i_satl0 are the initial values of i_sum, i_satu, and i_satl, respectively. By using Equation (35) to update the two limits, i_satu/i_sum remains constant when i_o varies. By substituting Equation (35) into Equation (33), the required duration becomes i_sum0/i_sum times its original value. Meanwhile, each phase current is i_sum/i_sum0 times its original value based on Equation (31). Furthermore, the depth of discharge of each ESU remains unchanged. Thus, Equation (34) is still fulfilled, and a smooth transition of the reference current is guaranteed.

When i_sum − i_satu − i_satl > i_satu, the phase currents are i_satu, i_satu, and i_sum – 2i_satu, respectively. When i_sum – i_satu – i_satl < i_satl, the phase currents are i_sum – 2i_satl, i_satl, and i_satl, respectively. In a similar way, Equations (33) and (34) can be calculated by replacing Equation (31). It can be further verified that the variable current limits formulated as Equation (35) are still effective for preventing step reference currents.

In addition, the reachable condition is also analyzed when i_o varies. On the one hand, i_satu/i_sum is constant with the variable i_satu. On the other hand, the ratio increases with a fixed i_satu because the accelerating factor and current limits are designed under full load. Thus, i_sum is lower than i_sum0, and Inequation (16) is always satisfied under load change.

To select proper i_satu for series applications, there are two key points. First, in order to remove the potential step reference currents, i_satu should not be too high, although a higher i_satu helps reduce the equalization time. Second, i_satu is designed to be proportional to i_sum in case the step reference currents occur under load change.

3.4. Theoretical Comparisons of Balancing Performance

In DSP28335 chips, the bit number of the analog-to-digital converter is 12, and the analog input voltage ranges from 0 to 3 V. The rated current of the adopted current sensor, LA50P, is 50 A. Through signal conditioning, 50 A is transformed to 3 V on DSP pins. As a result, 1 LSC = 50 A/(2¹² − 1) = 0.012 A, which is mentioned in Inequation (10). Based on the actual test, 1000 multiplications require about 170 us. This means t_mul is 0.17 us. When i_satu0 = 33 A, i_sum0 = 50 A, and t_else = 37 us in parallel applications, it can be derived that n $\le$ 54 based on Inequations (8) and (10), while n $\ge$ 9 based on Inequation (9). When i_satu0 = 33 A, i_satl0 = 6 A, _isum0 = 45 A, and t_else= 39 us in series applications, we can acquire that n$\ge$11 based on Inequation (14) and n$\le$64 based on Inequation (8). Furthermore, i_satuu was calculated as 24.2 A. The practical i_satu0 is adopted as 24 A for series applications. For fast convergence, n is set as 50 for both applications.

As shown in Figure 7, a numerical simulation was carried out to acquire theoretical curves under various conditions. For simplicity, power losses are ignored. Moreover, it is assumed that i_k follows its reference current immediately and u_ik is constant at its nominal value (12 V). Figure 8 gives the theoretical curves when the proposed strategy is used in parallel scenarios. As seen in Figure 8a,d, the equilibrium point is not accessible if i_satu = 18 A because Inequation (16) is not fulfilled. In addition, a higher i_satu contributes to shorter balancing duration because higher current deviations enable a faster approaching speed of SoC levels. As Figure 8b,e exhibit, a larger n also helps to accelerate the balancing process among unsaturated ESUs, but the improved effect is no longer remarkable if n is large enough. When load is reduced at 200 s and then restored at 1000 s, current balance and SoC equalization are still achieved. The relevant process is shown in Figure 8c,f.

Figure 9 displays the ideal waveforms when the proposed strategy is utilized in series scenarios. Figure 9a,d reveal that step reference currents are generated if i_satu > 24.2 A, e.g., i_satu = 30 A. If i_satu is fixed as 24 A under load variation, this may also lead to step reference current even if the load is restored. This is seen in Figure 9b,e. To fix this issue, a variable i_satu is applied. In Figure 9c,f, the undesired step references are avoided, and the corresponding balancing duration is not obviously lengthened.

In Figure 10, ESU#1 is the master unit. Here, i_satu is 33 A in parallel applications and 24 A in series applications, respectively. When ESU#2 is suddenly stopped (letting d₂ = 0), the SoC₂ is subsequently set to zero so that the energy of ESU#1 and ESU#3 can be redistributed for SoC balance. Under the proposed strategy, the balanced point is still reached between the rest units after a slave ESU exits the microgrids.

Battery degradation is commonly existent after numerous charge and discharge cycles. Furthermore, the usable capacity thereupon decreases. Thus, it is important to evaluate the effectiveness of the proposed strategy in such a scenario. Figure 11 exhibits the ideal curves when the proposed strategy is applied in a scenario wherein batteries degrade. Here, i_satu is 33 A in parallel applications and 24 A in series applications. Moreover, the three battery capacities, Q₁, Q₂, and Q₃, are 45 Ah, 38.4 Ah, and 41.7 Ah, respectively. The results show that this balancing method can still mitigate SoC deviations when battery capacities are inconsistent. Note that i₁, i₂, and i₃ are 16.2 A, 13.8 A, and 15 A, respectively, after SoC balance is achieved. In fact, they are proportional to the corresponding capacities of their own ESUs. In this case, the equal declining rate of SoC is shared by all ESUs and thus SoC balance can be maintained.

3.5. Design of a Dual-Loop Controller

The selection of controller parameters is vital to implement a control scheme. In fact, it directly influences the stability and dynamic performance of energy storage systems. Compared with other balancing methods, the main difference of the proposed strategy is the voltage loop after CDRs are introduced. A simplified control diagram of the k-th unit is outlined in Figure 12. Typical PI regulators are applied for both voltage and current control. In parallel applications, the transfer functions from d_k to i_k, G_idk and from i_k to u_dc, G_vik are formulated as

$$G_{idk}=\frac{u_{ik}(RCs+2)}{[L_{k}CR{s}^2+L_{k}s+mR{(1-d_k)}^2](1-d_k)}$$

(36)

$$G_{vik}=\frac{mR{(1-d_k)}^2-s{L}_k}{(1-d_k)(RCs+2)}$$

(37)

As u_ik varies little during discharge, it is considered to equal 12 V, which is the nominal battery voltage.

The adopted controller parameters are shown in Table 2. A bode diagram of the open current loop is given in Figure 13a, and w_c is the cut-off frequency. The stability margin of the inner loop is at least 83° and w_c is at least 370 rad/s when R ranges from 3 Ω to 1.5 Ω. The upper and lower limits of the CDR are 0.66 and 0.00024, which correspond to 33 A (i_satu in parallel applications) and 0.012 A (1 LSC in Inequation (10)). There are usually deviations between the real and nominal resistances. Similar phenomena also occur for the inductance and capacitance in actual converters. In addition, the CDR of each unit gradually varies until SoC balance is achieved. Therefore, the abovementioned cases were all considered when choosing k_pv and k_iv. Sufficient stability margins are effective solutions to mitigating these issues. For conventional applications, the phase margin is usually designed to be no less than 45 degrees. In order to ensure stable operation under CDR variations and mismatches of circuit parameters, the phase margin is enhanced to no less than 70 degrees in this paper. In Figure 13b, the magnitude and phase response curves under several boundary conditions are depicted. The expected phase margins are acquired. Although the voltage-loop w_c is low, it is acceptable, as the guaranteed system stability is a prerequisite for balancing control.

As for series applications, the values of the control parameters are the same. The procedures for controller design are similar and have been omitted for convenience.

4. Experimental Verification

4.1. Experimental Platform

The configuration of the experimental platform is given in Figure 14, and the practical prototype is shown in Figure 15. The system parameters are shown in Table 2. IRFP4668PBF-type MOSFETs were used as power switches and diodes. The upper arm of the half bridge was kept off, while the lower arm was controlled by a PWM signal. Then, the boost converter was designed in such a manner. For simplicity, all the current loops share the same control parameters.

To accomplish dual-loop control, the feedback signal of inductor current was sent to its own DSP, while the sensing signal of u_dc was addressed by DSP#1 (master) to conduct voltage regulation. The resulting reference current was also calculated there and subsequently shared through a controller area network (CAN). Detailed communication variables are presented in

Table 4. Communication variables.

Communication	Transmission	Reception	Involved Variables
CAN	DSP#1	DSP#2	isum, ${SoC}_1^n$, ${SoC}_3^n$,
	DSP#2	DSP#1	${SoC}_2^n$, SoC2, i2
	DSP#1	DSP#3	isum, ${SoC}_1^n$, ${SoC}_2^n$
	DSP#3	DSP#1	${SoC}_3^n$, SoC3, i3
RS232	Labview	DSP#1	uref
	DSP#1	Labview	udc, i1, i2, i3 SoC1, SoC2, SoC3

. Considering that the balancing time is quite long, the overall process was recorded using LabVIEW 2018 software. In the RS232 style, the laptop receives the timing data package from DSP#1 and depicts waveforms in LabVIEW.

4.2. Testing Results and Analysis

First, the items of parallel applications without saturation were analyzed, and the related results are shown in Figure 16a,c. To validate the strategy without saturation in parallel applications, n was set to 8 to guarantee that the peak current was no higher than i_satu. To ensure that u_dc was constant, the phase currents were set to gradually increase as a result of a declining SoC and increasing inner resistances. The equilibrium point was reached at 3800 s. Subsequently, i_satu was adopted to accelerate the convergence of the balancing process, and n was increased to 50. The required time was about 1450 s according to Figure 17a,c. This corresponds to time savings of around 62% when current saturation is applied. After that, the experiment conducted under variable load (n = 50) was carried out. As Figure 17b displays, the load current was suddenly reduced by half at t = 200 s, while it returned to 20 A after a duration of 800 s. According to the testing data, equal SoC levels and currents were still realized, although the balanced point is delayed somewhat.

After that, the series application experiments were performed, and the corresponding outcomes are described in Figure 16b,d. To ensure that phase currents are between i_satu and i_satl, the proper value of n should be 5. Based on Figure 16b,d, it takes as long as 5630 s to accomplish SoC equalization and current balance without saturation because only a small n is utilized. To reduce the balancing time, current saturations were put into use. Figure 18 gives the testing results for when i_satu is 24 A and 33 A, respectively. In terms of the requisite seconds, there is no obvious difference. However, voltage fluctuation exists when i_satu is 33 A because excessive i_satu leads to a step change in the current reference. In contrast, a steady voltage can be maintained when i_satu is 24 A. To check the performance regarding variable i_satu, tests of load change were executed, and the results are shown in Figure 19. Fixed saturation of the step current reference may be not escapable even if it is elaborately designed. The original condition for preventing step change may no longer be satisfied, as the trajectories of the currents have altered (more or less). If the upper limit varies in proportion to the sum current, the abovementioned condition is always realizable, and Figure 19b gives proof for this.

Moreover, the slave ESU#2 suddenly stopped working on validating the feasibility of the proposed strategy when the number of slave units was reduced. Figure 20 depicts the entire process when the duty cycle of PCU#2 is disabled in series and parallel applications. Then, SoC₁ and SoC₃ could still be allowed to move towards each other by setting the corresponding variables of SoC₂ in the communication network as zero. Finally, equal SoC levels and balanced currents were still achieved between the remaining ESUs. The SoC₂ linearly decreases in series applications because the load current flows through ESU#2. However, SoC₂ remains unchanged in parallel applications because D₂ is turned off as a result of inverse voltage. After this point, i₂ becomes zero. The experimental results almost agree with the theoretical analysis, which proves the effectiveness of the proposed strategy.

Another two old batteries were used to carry out balancing control for the degradation condition. With the help of a battery tester, the actual levels of capacity reduction were obtained by measuring the internal resistance. The experimental waveforms of battery degradation are given in Figure 21. After the SoC levels had balanced, three currents were gradually increased to keep u_dc stable because the battery voltages decreased as a result of SoC decline. At the same time, it was satisfied that i₁/Q₁ ≈ i₂/Q₂ ≈ i₃/Q₃ after SoC errors were removed under the two kinds of applications. In other words, the ratio of steady current versus its own capacity was constant. With the proposed strategy, current sharing is realized when the battery capacities are match, so the balancing result with matched battery capacities can be seen as a special case of mismatched results.

The theoretical and actual balancing times required to achieve SoC consistency under different cases are collected in

Table 5. Theoretical and experimental comparisons of balancing time using the proposed strategy.

Case	Parallel Application			Series Application
	Theoretical	Actual	Deviation	Theoretical	Actual	Deviation
Normal operation	1700 s	1450 s	14.7%	2400 s	2200 s	8.3%
Load change	2050 s	1800 s	12.2%	2600 s	2550 s	1.9%
Battery degradation	1560 s	1500 s	3.8%	2620 s	2550 s	2.7%
Sudden termination	1600 s	1400 s	12.5%	2350 s	2250 s	4.3%

. To obtain the ideal curves, u_ik was assumed to be constant at 12 V to power the load in Section 3.4. Compared with the ideal time, the actual time was reduced. In the actual experiment, the battery voltages decreased and internal resistances increased during a long discharge, so d_k increases to keep u_dc unchanged and hence i_k gradually increased. With the same CDRs and circuit parameters, the higher the sum current, the shorter the duration required to eliminate SoC differences. In fact, this phenomenon contributes to the reduced balancing time.

To show the performance differences, experiments using the droop methods in reference [2] and [10] were further executed. The method in [2] is a typical voltage-type droop scheme, whose core expression is

$$u_{\mathrm{ref}\text{\_}k}=u_{\mathrm{ref}}-m_{0}So{C}_k^n\frac{u_{ok}{i}_{ok}}{u_{ik}}$$

(38)

where u_{ref_k}, u_ok, and i_ok are the reference voltage, output voltage, and output current of the k-th unit, respectively. In [10], the current-type droop method is denoted as

$$i_{\mathrm{r}k}=(u_{\mathrm{ref}}-u_{\mathrm{dc}})m_{1}So{C}_k^n$$

(39)

where m₀ and m₁ are the initial droop coefficients, which must be properly chosen to prevent obvious voltage deviations. In [2], n was set as 8 in case the power of ESU#1 exceeded its allowable upper limit. A small m₀ helps to reduce the deviation of u_dc, and it is 1 × 10⁻⁵ here. In [10], i_satu was 33 A, and n was 50. A large m₁ leads to a lower voltage drop of u_dc, and it was set to 1 × 10⁹. If m₁ is larger than 1 × 10⁹, the system will be unstable. The related waveforms are presented in Figure 22. Affected by the mismatched power losses and line resistances in real circuits, the ESU with the highest SoC does not deliver the highest current in the primary stage. Based on Equations (38) and (39), u_dc gradually declines regardless of whether [2] or [10] is adopted because each SoC level persistently decreases when the discharge continues. The comparative indexes are summarized in

Table 6. Experimental performance comparisons of different methods.

Balancing Scheme	Balancing Duration	Final SoC Deviation
[2]	over 6000 s (Figure 22c)	around 0.9% (Figure 22e)
[10]	over 2300 s (Figure 22d)	around 0.3% (Figure 22f)
proposed	1450 s (Figure 17a)	around 0.1% (Figure 17c)

. In contrast with [2] and [10], the results of the proposed strategy in Figure 17a,c display faster balancing speed because the voltage deviation is inexistent; hence, the sum current is always higher than that in the droop methods. Furthermore, a higher sum current leads to a faster mitigation of SoC differences with the same CDRs and circuit parameters. As for equalization precision, the proposed method removes the influence of actual power losses and u_ik decline, so it is more accurate. In [2] and [10], the SoC in real time is based on approximate estimation. However, the actual SoC during discharge is always lower than its approximate value used in microprocessor programs because ESUs must deliver higher currents to make up for power losses. Furthermore, the mismatched power losses of each unit enlarge the final SoC deviations between the highest and lowest SoC values. The corresponding results are shown in Table 6.

5. Conclusions

For the ESUs interfacing with boost converters, a fast balancing strategy based on CDRs was designed to eliminate the SoC differences during the discharge process. It is feasible for both parallel and series applications. Instead of energy conservation, accurate SoC estimation and equalization are achieved without the need for extra sensors. Moreover, the balancing duration was remarkably shortened by introducing current saturations into the CDRs. In consideration of the actual execution time, the least significant current, and high current deviation, the accelerating factors in the CDRs were separately chosen for two kinds of applications. Furthermore, the current limits were reasonably selected to reach an equilibrium point and avoid a step reference current. Moreover, the controllers of the dual-loop system were designed to account for enough stability margins. The experimental results obtained under different operating conditions have proven the effectiveness of the proposed strategy. However, this strategy is not feasible at present if the ESUs operate in the charging process or communication fails. Thus, determining how to enhance its reliability and usability will be our concern in the future.