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Inicio  /  Computation  /  Vol: 10 Par: 10 (2022)  /  Artículo
ARTÍCULO
TITULO

Power Loss Minimization and Voltage Profile Improvement by System Reconfiguration, DG Sizing, and Placement

Mlungisi Ntombela    
Kabeya Musasa and Moketjema Clarence Leoaneka    

Resumen

A number of algorithms that aim to reduce power system losses and improve voltage profiles by optimizing distributed generator (DG) location and size have already been proposed, but they are still subject to several limitations. Hence, new algorithms can be developed or existing ones can be improved so that this important issue can be addressed more appropriately and effectively. This study proposes a reconfiguration methodology based on a hybrid optimization algorithm, consisting of a combination of the genetic algorithm (GA) and the improved particle swam optimization (IPSO) algorithm for minimizing active power loss and maintaining the voltage magnitude at about 1 p.u. The buses at which DGs should be injected were identified based on optimal real power loss and reactive power limit. When applying the proposed optimization algorithm for DGs allocation in power system, the search space or number of iterations was reduced, increasing its convergence rate. The proposed reconfiguration methodology was test in an IEEE-30 bus electrical network system with DGs allocations and the simulations were conducted using MATLAB software compared to other optimization algorithms, such as GA, PSO, and IPSO, the combination of GA and IPSO or Hybrid GA & IPSO (HGAIPSO) method has a smaller number of iterations and is more effective in optimization problems. The effectiveness of the proposed HGAIPSO has been tested on IEEE-30 bus network system with DGs allocations, and the obtained test results have been compared to those from other methods (i.e., GA, PSO, and IPSO). The simulation results show that the proposed HGAIPSO can be an efficient and promising optimization algorithm for distribution network reconfiguration problems. The IEEE-30 bus test system with DGs integrated at various location revealed reductions in overall real power loss of 40.7040%, 36.2403%, and 42.9406% for type 1, type 2, and type 3 DGs allocation, respectively. The highest bus voltage profile goes to 1.01 pu in the IEEE-30 bus.

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