Resumen
Processors with a domain-specific instruction set (ASIP, application-specific instruction set processor) are used today more and more widely. They are used in such areas as machine learning, image processing and cryptography. Due to the specialization of the architecture for solving problems from narrow domain areas the domain-specific processors can be more attractive than general-purpose processors in terms of, for example, characteristics such as energy efficiency. At the same time, due to the feature of programmability, domain-specific processors may be preferable to ASIC solutions.One important task is to achieve a high developing speed of domain-specific instruction sets for solving problems from various domain areas. The paper proposes an iterative approach to the synthesis and modeling of a domain-specific instruction set based on the analysis of the dependency graph of the application at the basic block level, as well as using a set of architectural constraints. Basic RISC-like operations are combined into composite CISC operations. The parallelism of operations is revealed, including taking into account memory accesses, for instruction sets of VLIW type. For the practical evaluation of this approach, a compiler backend module has been developed. The results of synthesis and modeling of instruction sets for program tests selected from several domain areas are demonstrated.