Resumen
The LinoSPAD camera system is a modular, compact and versatile time-resolved camera system, combining a linear 256 high fill factor pixel CMOS SPAD (single-photon avalanche diode) sensor with an FPGA (field-programmable gate array) and USB 3.0 transceiver board. This modularization permits the separate optimization or exchange of either the sensor front-end or the processing back-end, depending on the intended application, thus removing the traditional compromise between optimal SPAD technology on the one hand and time-stamping technology on the other hand. The FPGA firmware implements an array of 64 TDCs (time-to-digital converters) with histogram accumulators and a correction module to reduce non-linearities. Each TDC is capable of processing over 80 million photon detections per second and has an average timing resolution better than 50 ps. This article presents a complete and detailed characterization, covering all aspects of the system, from the SPAD array light sensitivity and noise to TDC linearity, from hardware/firmware/software co-design to signal processing, e.g., non-linearity correction, from power consumption to performance non-uniformity.